1. Field of the Invention
The present invention relates to field programmable gate arrays, and more particularly, to a field programmable gate array incorporating configurable function blocks, each one separately configurable as either high performance programmable logic or a block of SRAM.
2. Art Background
Programmable logic chips can take many forms. One such form is commonly referred to as a programmable logic device, or "PLD." Most programmable logic devices (PLD's) are internally structured as variations on an architecture which utilizes a programmable logic array. A programmable logic array makes use of the fact that any logic equation can be converted into an equivalent "sum-of-products" form and thus implemented through the use of interconnected "AND" and "OR" gates. The programmable logic array architecture utilizes programmable connections such that a user can selectively determine the inputs into an array of "AND" gates connected to an array of "OR" gates. The architecture of a PLD utilizing a programmable logic array also typically includes feedback options which allow the user greater flexibility to implement sequential logic functions.
The programmable connections in a PLD using a programmable logic array architecture are fixed in number and location within the logic array. However, whether these programmable connections are in an open or closed state is determined by the user of the PLD. In particular, the user programs the PLD by specifying which of these connections he would like to remain open, and which he would like to close. Programmability, it will be appreciated, allows for instant customization, very similar to user programmable memories such as PROM's or EPROM's. In effect, a user can purchase a PLD chip off-the-shelf, use a programming system running, for example, on a personal computer, and in a matter of a few hours, have a customized logic chip in his hands. Using a PLD can advantageously reduce the chip count needed to implement logic, saving board space and resulting in smaller system physical dimensions. A reduced chip count can additionally contribute to faster system speeds, lower power consumption, and higher reliability. A PLD can further provide for increased flexibility, allowing the user to upgrade the system without rendering the logic obsolete. In such circumstances, the PLD is simply reprogrammed.
A second form of programmable logic chip, a field programmable gate array, or "FPGA," comprises a number of programmable logic blocks coupled together with means for selectively routing signals to and from the programmable logic blocks. The number and nature of the programmable logic blocks, as well as the means chosen for selectively routing signals to and from the programmable logic blocks is dependent upon the particular architecture chosen for the FPGA. In the past, FPGA's have not provided particularly fast logic, typically running in the 10-20 MHz range. As a result, prior art FPGA's have often been used in the peripheral areas of computer systems to integrate logic otherwise requiring numerous PLD chips, onto a single FPGA chip.
As will be described, the present invention provides for a high performance FPGA chip incorporating a plurality of configurable function blocks coupled to a global interconnect matrix. Each one of these configurable function blocks incorporates a volatile logic array architecture based upon static random access memory (SRAM). In accordance with the apparatus and method of the present invention, each one of these function blocks is configurable as either high performance programmable logic or a block of SRAM which the user can then write to, and read from, as he would a conventional block of SRAM.